The PCI Express 3.0 standard has been with us rather longer than anyone intended it to be. The standard was initially finished in 2010, and motherboards supporting it were in-market by 2011. PCI Express 4.0 should have been available by 2013 if the organization had kept to its previous pace, but delays and difficulties associated with the design have left PCIe 4.0 support languishing. Now PCI-SIG has announced that PCIe 4.0 specification is finished — and it plans to have PCIe 5.0 ready to go by 2019.
That’s an accelerated launch window and, given the relatively short window between completing the standard and shipping hardware (typically about 12 months), it’s not clear if PCIe 4.0 will find a huge home in the market. PCIe 5.0, according to the standards body, is coming along quite quickly.
“In our 25-year history, PCI-SIG has maintained its commitment to our rigorous specification development process, while delivering specifications that are in lock-step with industry requirements for high-performance I/O,” said Al Yanes, PCI-SIG Chairman and President. “PCIe 5.0 technology is the next evolution that will set the standard for speed, and we are confident that its 32GT/s bandwidth will surpass industry needs.”
The preceding PCIe 4.0 specification is designed with key functional enhancements that future-proof the PCIe architecture design, thereby accelerating speech and future design specifcations future specification development. This undertaking, along with improved silicon design processes, serves as the foundation for the PCIe 5.0 specification.
A quick progression from PCIe 4.0 to 5.0 might result in consumer hardware not shipping PCIe 4.0 for very long, but the 4x bandwidth increase for peripherals and devices would be huge.
With 64GB/s of unidirectional transfer bandwidth, PCIe 5.0 would deliver more bandwidth than dual-channel DDR3 interfaces. Heck, it would deliver more bandwidth than DDR4-3200, though at far higher latencies (nobody is going to be building PCIe-connected RAM any time soon). Even though GPUs are primarily the only devices that use x16 slots, quadruple the bandwidth per lane means that x1 and x4 products would still benefit from these gains. High-performance network and SSD solutions could both use the bandwidth, and PCIe 5.0 would put the industry ahead of even Nvidia’s high-speed NVLink technology.
With PCIe 4.0 only being finished now, we wouldn’t expect to see motherboard manufacturers integrating it until 2018, and that could take longer if AMD and Intel don’t bake support into their own upcoming products. Given that most CPUs have on-die PCI Express controllers these days, getting that kind of capability baked into hardware refresh cycles rests more on the CPU vendor than motherboard company, though the mobo manufacturers do need to do the work of validating their board designs. If PCI-SIG hits its target goal of a 2019 standard finalization date, PCIe 5.0 could be in-market by 2020 or 2021.
source : https://www.extremetech.com/computing/250640-pci-sig-announces-plans-launch-pcie-5-0-2019-4x-bandwidth-pcie-3-0